Digital electronic devices such as microprocessors often contain numerous components that may perform sub-functions for the device. For example, the arithmetic logic unit (ALU) of a microprocessor typically contains one or more adders that receive a number of digital inputs and that output the sum of these inputs. As another example, an electronic device may contain multipliers that receive a number of digital inputs and output the result of a multiplication function performed on these inputs. Digital circuits such as adders and multipliers may themselves be made up of smaller digital circuits or logic gates such as, for example, a reducer. A reducer receives a number of input bits and provides sum and carry bits as outputs. For example, a three-to-two reducer may receive three input bits and provide a sum bit (i.e., the sum of the three input bits) and a carry bit (indicating if the addition of the three input bits generates a carry out) as outputs. A four-to-two reducer may receive four input bits and provide a sum bit and carry bit as outputs. As would be appreciated by a person of skill in the art, such a four-to-two reducer may also receive a carry in bit and provide an intermediate carry out bit (which may be absorbed by a neighboring four-to-two reducer), but such bits are not counted as part of the “four-to-two” because for counting purposes they cancel each other out.
The component circuits in digital devices often use domino logic. A domino circuit is a type of circuit that is arranged in stages (e.g., logic gates) with the outputs from one stage used as inputs into the next stage. The clock used with a domino circuit typically is delayed for each of the individual stages to provide a set-up time for the stages. The individual domino logic gates typically have one or more precharge blocks, which force the circuit to a known state during a precharge phase of a clock, and one or more evaluation blocks, which provide output values during an evaluation phase of the clock. Domino circuits generally have a static stage in between the domino stages. For example, the domino circuit may have an inverter between the domino stages or a static complimentary metal-oxide semiconductor (CMOS) gate between the domino stages. Another example is the zipper domino circuit, which has a P-channel metal-oxide semiconductor (PMOS) gate between the domino stages. In a cascaded domino circuit, the outputs from one N-channel metal-oxide semiconductor (NMOS) domino gate (i.e., a gate with NMOS transistors in the evaluation block) are directly connected to the inputs of another NMOS domino gate. Thus, a cascaded domino circuit does not have any invertors, static stages, or PMOS gates in the critical path of the logic.
Four-to-two reducers have not been constructed as cascaded domino circuits. Domino four-to-two reducers have been constructed by using three-to-two reducers, but such four-to-two reducers have used static CMOS stage(s) of logic between the three-to-two reducers. The static stages in these prior four-to-two reducers have an effect on the clocking of the circuit and, as is known in the art, a circuit may not operate correctly if it is not adequately sequenced. Thus, a topology for adequately sequencing a domino four-to-two reducer without static stages has not been known.